PIC18F26J50-I/ML【PDF 14/32 页】IC PIC MCU FLASH 64K 2V 28-QFN

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Sheet目录3858

10页 11页 12页 13页 [14页]15页 16页 17页 18页

2009 Microchip Technology Inc.

DS39687E-page 21

PIC18F2XJXX/4XJXX FAMILY

CPDIV<1:0>(3)

CONFIG1H

CPU System Clock Selection bits

11 = No CPU system clock divide

10 = CPU system clock divided by 2

01 = CPU system clock divided by 3

00 = CPU system clock divided by 6

IESO

CONFIG2L(1,2)

Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Oscillator Switchover mode enabled

0 = Oscillator Switchover mode disabled

FCMEN

CONFIG2L(1,2)

Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

LPT1OSC

CONFIG2L(1,2)

Low-Power Timer1 Oscillator Enable bit

1 = Timer1 oscillator configured for low-power operation

0 = Timer1 oscillator configured for higher power operation

T1DIG

CONFIG2L(1,2)

Secondary Clock Source T1OSCEN Enforcement bit(1)

1 = Secondary oscillator clock source may be selected (OSCCON <1:0> = 01)

regardless of T1OSCEN state

0 = Secondary oscillator clock source may not be selected unless T1CON <3> = 1

FOSC<2:0>

CONFIG2L(1,2)

Oscillator Selection bits

111 = EC+PLL (S/W controlled by PLLEN bit), CLKO on RA6

110 = EC oscillator (PLL always disabled) with CLKO on RA6

101 = HS+PLL (S/W controlled by PLLEN bit)

100 = HS oscillator (PLL always disabled)

011 = INTOSCPLLO, internal oscillator with PLL (S/W controlled by PLLEN bit), CLKO

on RA6, port function on RA7

010 = INTOSCPLL, internal oscillator with PLL (S/W controlled by PLLEN bit), port

function on RA6 and RA7

001 = INTOSCO, internal oscillator, INTOSC or INTRC (PLL always disabled), CLKO on

RA6, port function on RA7

000 = INTOSC, internal oscillator INTOSC or INTRC (PLL always disabled), port function

on RA6 and RA7

WDTPS<3:0>

CONFIG2H(1,2) Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

TABLE 5-5:

PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F46J11 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP Bulk Erase operation.

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